Point-to-point interconnects between two ICs (Integrated Circuits) or ASICs (Application Specific Integrated Circuits) are becoming a widely accepted bus technology for high speed data transfer applications. The signaling scheme for such links can be single-ended or differential. Inter-symbol interference (ISI) due to the interconnect frequency dependent insertion loss characteristics becomes an even larger problem with current printed circuit board (PCB) technology. ISI is one of the primary bottlenecks in implementation of point-to-point high speed interconnection technology.
Various on-die receiver equalization techniques can be used to reduce the inter-symbol interference (ISI) generated by the frequency dependent loss characteristics of PCB traces. Some known receiver equalization techniques include equalization schemes with a digital filter and equalization schemes with an active linear filter.
Receiver equalization techniques using a digital filter use an appropriate active digital FIR filter (finite impulse response filter) or an IIR filter (infinite impulse response filter) at the receiver end to cancel out the frequency dependent loss characteristics. One example of such a digital filter is an adaptive-tapped-delay-line-filter implemented at the receiver end. Digital filter receiver equalization techniques at the receiver end are advantageous, but difficult to implement in silicon. Digital filter receiver equalization circuits using FIR or IIR filters dissipate a lot of power. The coefficient of such a digital adaptive filter can be determined using a suitable training sequence and a high order filter scheme is possible, but implementation is extremely complex. It is difficult to obtain gain during implementation of this stage due to limited available voltage headroom.
Equalization schemes with an active linear filter is easy to implement and circuits using these schemes are able to dissipate power appropriately. Additionally, interconnects with a large loss can be equalized. This can lead to use of longer length interconnects. However, active filters are typically implemented using gm-c circuit elements, which have limited bandwidth.